The present invention relates to programmable logic devices generally and, more particularly, to a programmable logic device architecture that may improve functionality over look-up table based or product-term based programmable logic devices and that may provide for the efficient implementation of user-programmable logic designs resulting in implementations that may require less area and may provide increased performance.
Field programmable gate arrays (FPGAs) typically consist of arrays of programmable macrocells (or arrays of clusters of programmable macrocells) and a programmable routing network. The programmable routing network is used to route signals between macrocells, between clusters of macrocells, and between the I/Os and macrocells. FPGA macrocells may contain one or more look-up tables (LUTs), a flip-flop, one or more programmable multiplexers, and control logic for flip-flop control signals, as well as carry chain and cascade chain logic.
Referring to FIG. 1, one conventional FPGA macrocell 10 is shown comprising a look-up table 12, a look-up table 14, a look-up table 16, a number of configuration multiplexers 18a-18n, a flip-flop 20, and a flip-flop 22. The FPGA macrocell 10 is sometimes referred to as a logic element, a logic cell, a programmable function unit, a configureable logic block or other similar name.
Referring to FIG. 2, a portion of a typical FPGA 30 is shown made up of a number of FPGA macrocells 10a-10n. Programmable routing channels (34a-34n) are located between the FPGA macrocells 10a-10n and can be used to propagate signals from one of the macrocell 10a-10n to another and between input/output (I/O) and the macrocells 10a-10n. FIG. 3 illustrates a routing matrix 40 that can be implemented to produce the inputs to the various macrocells 10a-10n. 
Logic functions are implemented in FPGA macrocell 10 by using (i) synthesis and technology mapping software to map logic into the macrocells, (ii) placement software to determine where to place logic within the array, and (iii) routing software to route the necessary signals in the programmable routing network.
Referring to FIG. 4, another macrocell 50 in accordance with conventional methods shown. The macrocell 50 generally comprises a look-up table 52, a flip-flop 54, output multiplexers 56a and 56b, a carry chain logic 58, flip-flop control logic 60 and a clock select multiplexer 62. FIG. 5 illustrates a clustered logic block 51 comprising macrocells 50a-50n and a local programmable routing network. FIG. 6 illustrates an array of clustered logic blocks 51a-51n illustrating a portion of an FPGA along with an associated routing network.
Presently, complex programmable logic devices (CPLD) may contain a programmable routing network, multiple blocks comprising a product term array, a product term matrix, a number of OR-gates, and macrocells. The macrocells are comprised of a programmable flip-flop, programmable multiplexers, and sometimes an XOR gate or carry logic.
Logic functions are implemented in the CPLD by using synthesis and technology mapping software to map logic to the product-term array and associated macrocells. Partitioning and placement software is used to determine where to place logic within the CPLD.
Some conventional approaches have defined the terms FPGA and CPLD in different ways. In general, the distinction between FPGAs and CPLDs is blurring as both devices move to higher densities. For illustrative purposes, FPGAs will be considered to use LUTs as the basic building-block for implementing logic, and CPLDs will be considered to use product terms (e.g., programmable AND-OR planes) as the basic building block for implementing logic.
Some disadvantages of the LUT-based macrocell are that a LUT can only implement functions of up to the number of inputs to the LUT (usually between 3 and 5, inclusive). Complex functions usually must be implemented using a number of macrocells. Some commonly required functions cannot be efficiently implemented in just one macrocell. Functions requiring multiple macrocells utilize the macrocells inefficiently, wasting logic, routing resources, and die area, while degrading the performance of the implemented circuit.
One disadvantage of product-term based CPLDs with macrocells (e.g., where the input to a macrocell is an OR function of multiple product terms) is that some functions (e.g, a multiple input XOR function) often cannot be implemented efficiently in AND-OR logic. Arithmetic functions such as adders, subtractors, comparators, and parity trees are examples of functions that are not implemented efficiently with AND-OR logic.
The present invention concerns a programmable device architecture that may improve functionality over look-up table based or product-term based programmable logic devices and that may provide for the efficient implementation of user-programmable logic designs resulting in implementations that may require less area and may provide increased performance. A product-term array (either fully or partially populated) may be placed in front of a number of LUT-based macrocells, utilizing the available routing wires as wordlines to form the product terms. The present invention takes advantage of existing routing to do more than just route signals from one point to another by allowing logic to be implemented in the same die area. The result is logic implementations that may require fewer total macrocells, fewer levels of macrocells, and fewer point-to-point nets (because logic density increases). The present invention may apply to FPGAs comprising an array of macrocells and to FPGAs comprising an array of clustered macrocells. The present invention may also be used with CPLDs by replacing or supplementing the product term matrix, OR gates, and macrocells with LUT-based macrocells. The present invention may be used to implement logic functions in fewer macrocells than may be implemented in either LUT-based macrocells or product-term based macrocells alone.
The objects, features and advantages of the present invention include providing a product-term array with a look-up table-based macrocell in a FPGA or a CPLD that improves the area efficiency in implementing user designs as well as the speed of operation of the user designs.